The memory sitting next to an AI processor may eventually move upstairs. You see, Samsung has revealed a new memory architecture called zHBM, which would place high-bandwidth memory directly above an AI accelerator. The concept could reduce the distance data must travel between the processor and memory, potentially improving performance while using less power.
The company introduced zHBM at Future of Memory and Storage 2026 in Santa Clara, California. It also showed zNAND-O, a NAND design aimed at edge AI systems, and V10 BV-NAND with more than 400 layers.
Of those announcements, zHBM is the most interesting. Current AI accelerators generally place HBM packages beside the processor on the same substrate. That arrangement is already much faster than relying on conventional system memory, but data still has to move horizontally between the processor and the HBM stacks.
Samsung’s concept moves the memory above the accelerator instead. Shortening that connection could increase bandwidth, lower latency, and reduce the energy consumed while moving enormous amounts of data.
This matters because memory has become one of the biggest constraints in AI infrastructure. Faster processors only help when memory can supply them with data quickly enough. As AI models grow, so does the pressure on bandwidth, capacity, cooling, and power consumption.
Samsung claims a future zHBM interface could provide approximately eight times the performance of HBM5. The company also says wafer bonding could deliver more than 10 times the memory density, three times the energy efficiency, and less than half the thermal resistance.
Those figures sound impressive, but they are still projections. Samsung is presenting zHBM as a concept architecture, not a finished product that customers can buy. There are no independent benchmarks, pricing details, or launch dates.
Placing memory above a powerful AI processor also creates obvious engineering challenges. Heat is already difficult to manage inside dense accelerator packages, and adding more silicon vertically could complicate cooling and manufacturing. Samsung says its bonding technology can reduce thermal resistance, but that claim will matter only if the design reaches production.
The architecture could also allow customers to place customized intellectual property in an interlayer between the memory and accelerator. That could lead to packages tailored for specific AI workloads instead of forcing every customer to use the same configuration.
Samsung did not say when zHBM might become a commercial product. For now, it shows how the company expects AI memory packaging to evolve beyond HBM5.
The company also introduced zNAND-O, which applies a layered design to NAND flash. Samsung is developing four-layer and eight-layer versions for edge AI systems that require low latency and high input and output performance.
Its more immediate announcement is V10 BV-NAND, a new Bonding V-NAND architecture with more than 400 layers.
Rather than building every part of the NAND structure on a single wafer, Samsung bonds the memory cells to the peripheral components. The company says this increases memory density by approximately 58 percent compared with V9 while also improving read, write, and input and output performance.
Samsung used FMS 2026 to display a broader AI memory roadmap that included HBM4E, HBM5, LPDDR5X-PIM, and enterprise storage products such as the PM1763 and BM1773.
LPDDR5X-PIM performs some processing inside the memory itself. The goal is to reduce the constant movement of data between separate components, saving both time and electricity.
Samsung says it began mass-producing HBM4 in February 2026 and started shipping HBM4E samples to customers in May. It is already discussing HBM5 and zHBM, showing how quickly memory makers are planning beyond products that have barely reached the market.
There is plenty of marketing attached to Samsung’s announcement, especially around its claims of industry leadership. Still, the basic idea behind zHBM makes sense. AI processors need faster access to larger pools of memory, and simply placing more HBM beside an accelerator will not solve every packaging problem forever.
Stacking memory directly above the processor may be part of the answer. Samsung now has to prove that it can manufacture the design reliably, cool it effectively, and deliver something close to the performance it is promising.
Until then, zHBM is merely an intriguing concept rather than a product.
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